Background of the Invention
1. Field of the Invention
2. Description of the Related Technology
Summary of the Invention
Brief Description of the Drawings
Detailed Description of the Preferred Embodiments
I. Registered PCI Transaction Protocol
A. Overview of Registered PCI
B. Transaction Comparison Between Registered PCI and Conventional PCI
C. Registered PCI Transaction Protocol
1. Transaction Sequences
2. Allowable Disconnect Boundaries (ADB) and Buffer Size
3. Wait States
4. Addressing, Byte-Enables, and Alignment
5. Split Transactions
6. Bus Width
7. Source Sampling
8. Compatibility and System Initialization
D. Summary of Protocol Rules
1. Basic Initiator Rules
2. Basic Target Rules
3. Bus Arbitration Rules
4. Configuration Transaction Rules
5. Parity Error Rules
6. Bus Width Rules
E. Registered PCI Command Encoding
F. Registered PCI Extended Command Encoding
1. Validated Extended Command
2. Immediate Extended Command
G. Registered PCI Attributes
H. Byte-Count Transactions
1. Writes
2. Reads
I. Byte-Enable Transactions
1. Writes
2. Reads
J. Device Select Timing
1. Writes
2. Reads
K. Wait States
1. Writes
2. Reads
L. Configuration Transactions
M. Delayed Transactions
N. Split Transactions
1. Basic Split Transaction Requirements
2. Requirements for Accepting Split Completions
3. Split Completion Exception Message
4. Unexpected Split Completion Exceptions
O. Transaction Termination
1. Disconnect With Data
a. Initiator Termination and Disconnection
b. Target Disconnection
2. Target Retry Termination
a. Byte-Count Transactions
b. Byte-Enable Transactions
3. Split Response Termination
4. Master-Abort Termination
a. Byte-Count Transactions
b. Byte-Enable Transactions
5. Target-Abort Termination
a. Byte-Count Transactions
b. Byte-Enable Transactions
P. Bus Width
1. Data Transfer Width
2. Address Width
Q. Transaction Ordering and Deadlock-Avoidance
1. Ordering and Passing Rules
2. Required Acceptance Rules
R. Transaction Sequence Combining and Re-ordering
II. Arbitration
A. Arbitration Signaling Protocol
1. Starting a New Transaction
2. REQ# and GNT# Requirements
B. Arbitration Parking
III. Registered PCI Bridge Design Issues
A. Design Requirements for a Registered-PCI-to-Registered PCI Bridge
B. Design Requirements for a Registered-PCI-to-Conventional PCI Bridge
C. Bridge Error Handling
IV. Error Functions
A. Parity Generation
B. Parity Checking
C. Error Handling and Fault Tolerance
1. Data Parity Exception
2. Split Transaction Exceptions
V. Compatibility and System Initialization
A. Device Requirements
B. System Requirements
C. Frequency and Mode Initialization Sequence
1. Frequency and Mode Initialization Sequence in a Host Bridge
2. Frequency and Mode Initialization Sequence in a PCI-to-PCI Bridge
3. Hardware-Only Mode Switching Model
D. Interoperability Matrix
E. Hot Plug Events in a Registered PCI System
VI. Configuration Space
A. Registered PCI ID
B. Next Capabilities Pointer
C. Registered PCI Bridge Control
D. Registered PCI Command Register
E. Registered PCI Status Register
F. Memory Base Upper 32-Bits
G. Memory Base Limit Upper 32-Bits
VII. Electrical Specification
A. DC Specifications
B. AC Specifications
C. Maximum AC Ratings and Device Protection
D. Timing Specification
1. Clock Specifications
2. Timing Parameters
3. Measurement and Test Conditions
4. Device Internal Timing Examples
E. Clock Uncertainty
F. Reset
G. Pull-ups
H. Noise Budget
1. DC Noise Budget
2. Transient Noise Budget
I. System Timing
1. Timing Budget
J. Connector Pin Assignments
K. Power
1. Power Requirements
2. Sequencing
3. Decoupling
L. Expansion Board Trace Length and Signal Loading
M. Transmission Line Characteristics
VIII. Conventional PCI versus AGP 1.0 versus Registered PCI Protocol Rule Comparison
IX. Relaxed Ordering Rules
A. Background
B. System Topologies
1. Data and Trigger Near Writer
2. Data Near Writer, Trigger Near Reader
3. Data and Trigger Near Reader
4. Data Near Reader, Trigger Near Writer
C. I2O Usage Models
1. I2O Messaging Protocol Operation
2. Message Delivery with the Push Model
3. Message Delivery with the Pull Model
4. Message Delivery with the Outbound Option
5. Message Delivery with Peer to Peer
D. Rule Summary and Simplification
1. Field of the Invention
The present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), memory and computer peripherals together, and more particularly, in utilizing a registered peripheral component interconnect bus, logic circuits therefor and signal protocols thereof.
2. Description of the Related Technology
Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the computer has become an integral tool of most information workers who work in the fields of accounting, law, engineering, insurance, services, sales and the like. Rapid technological improvements in the field of computers have opened up many new applications heretofore unavailable or too expensive for the use of older technology mainframe computers. These personal computers may be used as stand-alone workstations (high end individual personal computers) or linked together in a network by a xe2x80x9cnetwork serverxe2x80x9d which is also a personal computer which may have a few additional features specific to its purpose in the network. The network server may be used to store massive amounts of data, and may facilitate interaction of the individual workstations connected to the network for electronic mail (xe2x80x9ce-mailxe2x80x9d), document databases, video teleconferencing, whiteboarding, integrated enterprise calendar, virtual engineering design and the like. Multiple network servers may also be interconnected by local area networks (xe2x80x9cLANxe2x80x9d) and wide area networks (xe2x80x9cWANxe2x80x9d).
Increasingly sophisticated microprocessors have revolutionized the role of the personal computer by enabling complex applications software to run at mainframe computer speeds. The latest microprocessors have brought the level of technical sophistication to personal computers that, just a few years ago, was available only in mainframe and mini-computer systems. Some representative examples of these new microprocessors are the xe2x80x9cPENTIUMxe2x80x9d and xe2x80x9cPENTIUM PROxe2x80x9d (registered trademarks of Intel Corporation). Advanced microprocessors are also manufactured by Advanced Micro Devices, Digital Equipment Corporation, Cyrix, IBM and Motorola. These sophisticated microprocessors have, in turn, made possible running more complex application programs that require higher speed data transfer rates between the central processor(s), main system memory and the computer peripherals.
Personal computers today may be easily upgraded with new peripheral devices for added flexibility and enhanced performance. A major advance in the performance of personal computers (both workstation and network servers) has been the implementation of sophisticated peripheral devices such as video graphics adapters, local area network interfaces, SCSI bus adapters, full motion video, redundant error checking and correcting disk arrays, and the like. These sophisticated peripheral devices are capable of data transfer rates approaching the native speed of the computer system microprocessor central processing unit (xe2x80x9cCPUxe2x80x9d). The peripheral devices"" data transfer speeds are achieved by connecting the peripheral devices to the microprocessor(s) and associated system random access memory through high speed expansion local buses. Most notably, a high speed expansion local bus standard has emerged that is microprocessor independent and has been embraced by a significant number of peripheral hardware manufacturers and software programmers. This high speed expansion bus standard is called the xe2x80x9cPeripheral Component Interconnectxe2x80x9d or xe2x80x9cPCI.xe2x80x9d A more complete definition of the PCI local bus may be found in the PCI Local Bus Specification, revision 2.1; PCI/PCI Bridge Specification, revision 1.0; the disclosures of which are hereby incorporated by reference. These PCI specifications are available from the PCI Special Interest Group, 2575 NE Kathryn St #17, Hillsboro, Oreg. 97124.
The PCI version 2.1 Specification allows for a 33 MHz or 66 MHz, 32 bit PCI bus; and a 33 MHz or 66 MHz, 64 bit PCI bus. The 33 MHz, 32 bit PCI is capable of up to 133 megabytes per second (xe2x80x9cMB/sxe2x80x9d) peak and 50 MB/s typical; and the 66 MHz, 32 bit PCI bus, as well as the 33 MHz 64 bit PCI bus, are capable of up to 266 MB/s peak. The PCI version 2.1 Specification, however, only allows two PCI device cards (two PCI connectors) on a 66 MHz PCI bus because of timing constraints such as clock skew, propagation delay, input setup time and valid output delay. Typically, the 66 MHz PCI version 2.1 Specification requires the sourcing agent to use a late-arriving signal with a setup time of only 3 nanoseconds (xe2x80x9cnsxe2x80x9d) to determine whether to keep the same data on the bus or advance to the next data, with a 6 ns maximum output delay. Current state of the art Application Specific Integrated Circuits (xe2x80x9cASICxe2x80x9d) using 0.5 micron technology have difficulty meeting the aforementioned timing requirements. Even using the newer and more expensive 0.35 micron ASIC technology may be marginal in achieving the timing requirements for the 66 MHz PCI bus.
Since the introduction of the 66 MHz timing parameters of the PCI Specification in 1994, bandwidth requirements of peripheral devices have steadily grown. Devices are beginning to appear on the market that support either a 64-bit bus, 66 MHz clock frequency or both, with peak bandwidth capabilities up to 533 Mbytes/s. Because faster I/O technologies such as Gigabit Ethernet and Fiberchannel are on the horizon, faster system-interconnect buses will be required in the future.
When an industry outgrows a widely accepted standard, that industry must decide whether to replace the standard or to enhance it. Since the release of the first PCI Specification in 1992, the PCI bus has become ubiquitous in the consumer, workstation, and server markets. Its success has been so great that other markets such as industrial controls, telecommunications, and high-reliability systems have leveraged the specification and the wide availability of devices into specialty applications. Clearly, the preferred approach to moving beyond today""s PCI Local Bus Specification is to enhance it.
What is needed is an apparatus, method, and system for a personal computer that provides increased data throughput between the personal computer system central processing unit(s), memory and peripherals that can operate at speeds significantly higher than today""s PCI Specification allows. In addition, the present invention shall still be compatible with and be able to operate at conventional PCI speeds and modes when installed in conventional computer systems or when interfacing with a conventional PCI device(s) or card(s).
The present invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing in a computer system a registered peripheral component interconnect bus, logic circuits therefor and signal protocols thereof. In the present invention, hereinafter referenced as Registered PCI (xe2x80x9cRegPCIxe2x80x9d), all signals are sampled on the rising edge of the PCI bus clock and only the registered version of these signals are used inside the RegPCI devices. In the current PCI 2.1 Specification, there are many cases where the state of an input signal setting up to a particular clock edge affects the state of an output signal after that same clock edge. This type of input-output signal behavior is not possible in a registered interface, thus RegPCI introduces the concept of a clock-pair boundary which replaces some single-clock-edges where control signals change. Timing on the RegPCI bus is not as critical as the aforementioned 66 MHz PCI 2.1 Specification, even when the RegPCI bus runs faster than 133 MHz. The RegPCI allows PCI bus operation with more than two PCI device cards.
RegPCI allows for higher clock frequencies such as, for example, 133 MHz in a fully backward-compatible way. RegPCI devices may be designed to meet Registered PCI requirements and still operate as conventional 33 MHz and 66 MHz PCI devices when installed in legacy computer systems. Similarly, if conventional PCI devices are installed in a RegPCI bus, the clock remains at a frequency acceptable to the conventional device, and other devices are restricted to using conventional protocol when communicating with the conventional device. It is expected that this high degree of backward compatibility will enable the gradual migration of systems and devices to bandwidths in excess of 1 Gbyte/s.
In the present invention, numerous combinations in control fields are reserved for new features. One such feature, Double Data Rate, has important application for the embedded controller designs and small slot-based systems. For that reason, control fields and signal protocols have been reserved for its implementation.
In the present invention, the peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. As with conventional PCI, a command is issued on a given clock cycle on the C/BE# portion of the PCI bus. The extended command and the attribute are issued on the PCI bus during the clock cycle immediately after the clock cycle when the initial command was issued. The second (extended) command is issued on the C/BE# portion of the PCI bus. The attribute is issued on the AD portion of the PCI bus. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems.
The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Extended command types define a path for the addition of new extended commands in the future. The extended commands establish a behavior for current devices when they encounter a reserved extended command. Reserved extended command encodings can be assigned in the future to new extended commands that will behave predictably with legacy devices. The attribute field is a 64-bit field that further defines and describes the transaction. The attributes appear in the clock following the address phase on the AD bus, contemporaneous with the issuance of the second (extended) command.
An embodiment of the invention contemplates a multiple use core logic chip set which may be one or more integrated circuit devices such as an Application Specific Integrated Circuit (xe2x80x9cASICxe2x80x9d), Programmable Logic Array (xe2x80x9cPLAxe2x80x9d) and the like. RegPCI device(s) may be embedded on the computer system motherboard, or may be on a separate card(s) which plugs into a corresponding card edge connector(s) attached to the system motherboard and connected to the core logic chip set through the RegPCI bus.
According to the PCI specification, including Registered PCI, all PCI devices shall implement a base set of configuration registers. The PCI device may also implement other required or optional configuration registers defined in the PCI specification. The PCI specification also defines configuration registers and information to be contained therein for a PCI compliant device so as to indicate its capabilities and system requirements. Once the information for all of the bus devices are determined, the core logic may be configured as an additional RegPCI bus interface by the startup software. This software also determines whether the PCI devices operate at 33 MHz or 66 MHz, have a 64 bit or 32 bit address and data bus, and if the PCI devices are RegPCI compliant.